Semiconductor device fabrication - Wikipedia

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuit (IC) chips such as modern computer ... Semiconductordevicefabrication FromWikipedia,thefreeencyclopedia Jumptonavigation Jumptosearch Manufacturingprocessusedtocreateintegratedcircuits Semiconductordevicefabrication MOSFETscaling(processnodes) 010 µm –1971 006 µm –1974 003 µm –1977  1.5 µm –1981 001 µm –1984 800 nm –1987 600 nm –1990 350 nm –1993 250 nm –1996 180 nm –1999 130 nm –2001 090 nm –2003 065 nm –2005 045 nm –2007 032 nm –2009 022 nm –2012 014 nm –2014 010 nm –2016 007 nm –2018 005 nm –2020 003 nm –2022 Future 002 nm ~2024 Half-nodes Density CMOS Device(multi-gate) Moore'slaw Transistorcount Semiconductor Industry Nanoelectronics vte NASA'sGlennResearchCentercleanroom ExternalimagePhotooftheinteriorofacleanroomofa300mmfabrunbyTSMC Semiconductordevicefabricationistheprocessusedtomanufacturesemiconductordevices,typicallyintegratedcircuit(IC)chipssuchasmoderncomputerprocessors,microcontrollers,andmemorychipssuchasNANDflashandDRAMthatarepresentineverydayelectricalandelectronicdevices.Itisamultiple-stepsequenceofphotolithographicandchemicalprocessingsteps(suchassurfacepassivation,thermaloxidation,planardiffusionandjunctionisolation)duringwhichelectroniccircuitsaregraduallycreatedonawafermadeofpuresemiconductingmaterial.Siliconisalmostalwaysused,butvariouscompoundsemiconductorsareusedforspecializedapplications. Theentiremanufacturingprocesstakestime,fromstarttopackagedchipsreadyforshipment,atleastsixtoeightweeks(tape-outonly,notincludingthecircuitdesign)andisperformedinhighlyspecializedsemiconductorfabricationplants,alsocalledfoundriesorfabs.[1]Allfabricationtakesplaceinsideacleanroom,whichisthecentralpartofafab.Inmoreadvancedsemiconductordevices,suchasmodern14/10/7 nmnodes,fabricationcantakeupto15weeks,with11–13weeksbeingtheindustryaverage.[2]Productioninadvancedfabricationfacilitiesiscompletelyautomatedandcarriedoutinahermeticallysealednitrogenenvironmenttoimproveyield(thepercentofmicrochipsthatfunctioncorrectlyinawafer),withautomatedmaterialhandlingsystemstakingcareofthetransportofwafersfrommachinetomachine.WafersaretransportedinsideFOUPs,specialsealedplasticboxes.AllmachineryandFOUPscontainaninternalnitrogenatmosphere.TheairinsidethemachineryandFOUPsisusuallykeptcleanerthanthesurroundingairinthecleanroom.Thisinternalatmosphereisknownasamini-environment.[3]FabricationplantsneedlargeamountsofliquidnitrogentomaintaintheatmosphereinsideproductionmachineryandFOUPs,whichisconstantlypurgedwithnitrogen.[4] Contents 1Size 2History 2.120thcentury 2.221stcentury 3Listofsteps 4Preventionofcontaminationanddefects 5Wafers 6Processing 6.1Front-end-of-line(FEOL)processing 6.1.1Gateoxideandimplants 6.2Back-end-of-line(BEOL)processing 6.2.1Metallayers 6.2.2Interconnect 7Wafertest 8Devicetest 9Deviceyield 10Diepreparation 11Packaging 12Hazardousmaterials 13TimelineofcommercialMOSFETnodes 14Seealso 15References 16Furtherreading 17Externallinks Size[edit] Aspecificsemiconductorprocesshasspecificrulesontheminimumsizeandspacingforfeaturesoneachlayerofthechip.[5] Oftenanewersemiconductorprocesseshassmallerminimumsizesandtighterspacingwhichallowasimpledieshrinktoreducecostsandimproveperformance.[5]partlyduetoanincreaseintransistordensity(numberoftransistorspersquaremillimeter). Earlysemiconductorprocesseshadarbitrary[citationneeded]namessuchasHMOSIII,CHMOSV; lateronesarereferredtobysizesuchas90nmprocess. Byindustrystandard,eachgenerationofthesemiconductormanufacturingprocess,alsoknownastechnologynode[6]orprocessnode,[7][8]isdesignatedbytheprocess’sminimumfeaturesize.Technologynodes,alsoknownas"processtechnologies"orsimply"nodes",aretypicallyindicatedbythesizeinnanometers(orhistoricallymicrometers)oftheprocess'transistorgatelength.However,thishasnotbeenthecasesince1994.Initiallytransistorgatelengthwassmallerthanthatsuggestedbytheprocessnodename(e.g.350 nmnode);howeverthistrendreversedin2009.[9]Thenanometersusedtonameprocessnodeshasbecomemoreofamarketingtermthathasnorelationwithactualfeaturesizesnortransistordensity(numberoftransistorspersquaremillimeter).Forexample,Intel'sformer10 nmprocessactuallyhasfeatures(thetipsofFinFETfins)withawidthof7 nm,Intel'sformer10 nmprocessissimilarintransistordensitytoTSMC's7 nmprocesses,whileGlobalFoundries'12and14 nmprocesseshavesimilarfeaturesizes.[10][11][12] History[edit] Seealso:Listofsemiconductorscaleexamples,Moore'slaw,MOSintegratedcircuit,Semiconductorindustry,andTransistordensity 20thcentury[edit] AnimprovedtypeofMOSFETtechnology,CMOS,wasdevelopedbyChih-TangSahandFrankWanlassatFairchildSemiconductorin1963.[13][14]CMOSwascommercialisedbyRCAinthelate1960s.[13]RCAcommerciallyusedCMOSforits4000-seriesintegratedcircuitsin1968,startingwitha20 µmprocessbeforegraduallyscalingtoa10 µmprocessoverthenextseveralyears.[15] SemiconductordevicemanufacturinghassincespreadfromTexasandCaliforniainthe1960stotherestoftheworld,includingAsia,Europe,andtheMiddleEast. 21stcentury[edit] Thesemiconductorindustryisaglobalbusinesstoday.Theleadingsemiconductormanufacturerstypicallyhavefacilitiesallovertheworld.SamsungElectronics,theworld'slargestmanufacturerofsemiconductors,hasfacilitiesinSouthKoreaandtheUS.Intel,thesecond-largestmanufacturer,hasfacilitiesinEuropeandAsiaaswellastheUS.TSMC,theworld'slargestpureplayfoundry,hasfacilitiesinTaiwan,China,Singapore,andtheUS.QualcommandBroadcomareamongthebiggestfablesssemiconductorcompanies,outsourcingtheirproductiontocompanieslikeTSMC.[16]Theyalsohavefacilitiesspreadindifferentcountries. Since2009,"node"hasbecomeacommercialnameformarketingpurposesthatindicatesnewgenerationsofprocesstechnologies,withoutanyrelationtogatelength,metalpitchorgatepitch.[17][18][19]Forexample,GlobalFoundries'7 nmprocessissimilartoIntel's10 nmprocess,thustheconventionalnotionofaprocessnodehasbecomeblurred.[20]Additionally,TSMCandSamsung's10 nmprocessesareonlyslightlydenserthanIntel's14 nmintransistordensity.TheyareactuallymuchclosertoIntel's14 nmprocessthantheyaretoIntel's10 nmprocess(e.g.Samsung's10 nmprocesses'finpitchistheexactsameasthatofIntel's14 nmprocess:42 nm).[21][22] Asof2019,14nanometerand10nanometerchipsareinmassproductionbyIntel,UMC,TSMC,Samsung,Micron,SKHynix,ToshibaMemoryandGlobalFoundries,with7nanometerprocesschipsinmassproductionbyTSMCandSamsung,althoughtheir7 nanometernodedefinitionissimilartoIntel's10nanometerprocess.The5nanometerprocessbeganbeingproducedbySamsungin2018.[23]Asof2019,thenodewiththehighesttransistordensityisTSMC's5 nanometerN5node,[24]withadensityof171.3 milliontransistorspersquaremillimeter.[25]In2019,SamsungandTSMCannouncedplanstoproduce3nanometernodes.GlobalFoundrieshasdecidedtostopthedevelopmentofnewnodesbeyond12nanometersinordertosaveresources,asithasdeterminedthatsettingupanewfabtohandlesub-12 nmorderswouldbebeyondthecompany'sfinancialabilities.[26]Asof2019[update],Samsungistheindustryleaderinadvancedsemiconductorscaling,followedbyTSMCandthenIntel.[27] Listofsteps[edit] Thisisalistofprocessingtechniquesthatareemployednumeroustimesthroughouttheconstructionofamodernelectronicdevice;thislistdoesnotnecessarilyimplyaspecificorder.Equipmentforcarryingouttheseprocessesismadebyahandfulofcompanies.Allequipmentneedstobetestedbeforeasemiconductorfabricationplantisstarted.[28]Theseprocessesaredoneafterintegratedcircuitdesign. Waferprocessing Wetcleans Cleaningbysolventssuchasacetone,trichloroethyleneandultrapurewater Piranhasolution RCAclean Surfacepassivation Photolithography Ionimplantation(inwhichdopantsareembeddedinthewafercreatingregionsofincreasedordecreasedconductivity) Etching(microfabrication) Dryetching(Plasmaetching) Reactive-ionetching(RIE) Deepreactive-ionetching Atomiclayeretching(ALE) Wetetching Bufferedoxideetch Plasmaashing Thermaltreatments Rapidthermalanneal Furnaceanneals Thermaloxidation Chemicalvapordeposition(CVD) Atomiclayerdeposition(ALD) Physicalvapordeposition(PVD) Molecularbeamepitaxy(MBE) Laserlift-off(forLEDproduction[29]) Electrochemicaldeposition(ECD).SeeElectroplating Chemical-mechanicalpolishing(CMP) Wafertesting(wheretheelectricalperformanceisverifiedusingAutomaticTestEquipment,binningand/orlasertrimmingmayalsobecarriedoutatthisstep) Diepreparation Through-siliconviamanufacture(Forthree-dimensionalintegratedcircuits) Wafermounting(waferismountedontoametalframeusingDicingtape) Waferbackgrindingandpolishing[30](reducesthethicknessofthewaferforthindeviceslikeasmartcardorPCMCIAcardorwaferbondingandstacking,thiscanalsooccurduringwaferdicing,inaprocessknownasDiceBeforeGrindorDBG[31][32]) Waferbondingandstacking(ForThree-dimensionalintegratedcircuitsandMEMS) Redistributionlayermanufacture(forWLCSPpackages) WaferBumping(ForFlipchipBGA(Ballgridarray),andWLCSPpackages) DiecuttingorWaferdicing ICpackaging Dieattachment(Thedieisattachedtoaleadframeusingconductivepasteordieattachfilm[33][34]) ICbonding:Wirebonding,Thermosonicbonding,FlipchiporTapeAutomatedBonding(TAB) ICencapsulationorintegratedheatspreader(IHS)installation Molding(usingspecialMoldingcompoundthatmaycontainglasspowderasfiller) Baking Electroplating(platesthecopperleadsoftheleadframeswithtintomakesolderingeasier) Lasermarkingorsilkscreenprinting Trimandform(separatestheleadframesfromeachother,andbendstheleadframe'spinssothattheycanbemountedonaPrintedcircuitboard) ICtesting AdditionallystepssuchasWrightetchmaybecarriedout. Progressofminiaturization,andcomparisonofsizesofsemiconductormanufacturingprocessnodeswithsomemicroscopicobjectsandvisiblelightwavelengths. Preventionofcontaminationanddefects[edit] Mainarticle:Cleanroom Whenfeaturewidthswerefargreaterthanabout10micrometres,semiconductorpuritywasnotasbigofanissueasitistodayindevicemanufacturing.Asdevicesbecomemoreintegrated,cleanroomsmustbecomeevencleaner.Today,fabricationplantsarepressurizedwithfilteredairtoremoveeventhesmallestparticles,whichcouldcometorestonthewafersandcontributetodefects.Theceilingsofsemiconductorcleanroomshavefanfilterunits(FFUs)atregularintervalstoconstantlyreplaceandfiltertheairinthecleanroom;semiconductorcapitalequipmentmayalsohavetheirownFFUs.TheFFUs,combinedwithraisedfloorswithgrills,helpensurealaminarairflow,toensurethatparticlesareimmediatelybroughtdowntotheflooranddonotstaysuspendedintheairduetoturbulence.Theworkersinasemiconductorfabricationfacilityarerequiredtowearcleanroomsuitstoprotectthedevicesfromhumancontamination.Topreventoxidationandtoincreaseyield,FOUPsandsemiconductorcapitalequipmentmayhaveahermeticallysealedpurenitrogenenvironmentwithISOclass1levelofdust.FOUPsandSMIFpodsisolatethewafersfromtheairinthecleanroom,increasingyieldbecausetheyreducethenumberofdefectscausedbydustparticles.Also,fabshaveasfewpeopleaspossibleinthecleanroomtomakemaintainingthecleanroomenvironmenteasier,sincepeople,evenwhenwearingcleanroomsuits,shedlargeamountsofparticles,especiallywhenwalking.[35][36][37] Wafers[edit] Mainarticles:Wafer(electronics)andmono-crystallinesilicon Atypicalwaferismadeoutofextremelypuresiliconthatisgrownintomono-crystallinecylindricalingots(boules)upto300 mm(slightlylessthan12 inches)indiameterusingtheCzochralskiprocess.Theseingotsarethenslicedintowafersabout0.75 mmthickandpolishedtoobtainaveryregularandflatsurface. Processing[edit] Seealso:Waferfabrication Insemiconductordevicefabrication,thevariousprocessingstepsfallintofourgeneralcategories:deposition,removal,patterning,andmodificationofelectricalproperties. Depositionisanyprocessthatgrows,coats,orotherwisetransfersamaterialontothewafer.Availabletechnologiesincludephysicalvapordeposition(PVD),chemicalvapordeposition(CVD),electrochemicaldeposition(ECD),molecularbeamepitaxy(MBE),andmorerecently,atomiclayerdeposition(ALD)amongothers.Depositioncanbeunderstoodtoincludeoxidelayerformation,bythermaloxidationor,morespecifically,LOCOS. Removalisanyprocessthatremovesmaterialfromthewafer;examplesincludeetchprocesses(eitherwetordry)andchemical-mechanicalplanarization(CMP). Patterningistheshapingoralteringofdepositedmaterials,andisgenerallyreferredtoaslithography.Forexample,inconventionallithography,thewaferiscoatedwithachemicalcalledaphotoresist;then,amachinecalledastepperfocuses,aligns,andmovesamask,exposingselectportionsofthewaferbelowtoshort-wavelengthlight;theexposedregionsarewashedawaybyadevelopersolution.Afteretchingorotherprocessing,theremainingphotoresistisremovedby"dry"plasmaashing(photoresiststrippingorstrip).Thephotoresistmayalsoberemovedusingwetchemicalprocessesthatcoatthewaferinaliquidtoremovethephotoresist.[38] Modificationofelectricalpropertieshashistoricallyentaileddopingtransistorsourcesanddrains(originallybydiffusionfurnacesandlaterbyionimplantation).Thesedopingprocessesarefollowedbyfurnaceannealingor,inadvanceddevices,byrapidthermalannealing(RTA);annealingservestoactivatetheimplanteddopants.Modificationofelectricalpropertiesnowalsoextendstothereductionofamaterial'sdielectricconstantinlow-kinsulatorsviaexposuretoultravioletlightinUVprocessing(UVP).Modificationisfrequentlyachievedbyoxidation,whichcanbecarriedouttocreatesemiconductor-insulatorjunctions,suchasinthelocaloxidationofsilicon(LOCOS)tofabricatemetaloxidefieldeffecttransistors. Modernchipshaveuptoelevenormoremetallevelsproducedinover300ormoresequencedprocessingsteps. Front-end-of-line(FEOL)processing[edit] Mainarticle:FEOL FEOLprocessingreferstotheformationofthetransistorsdirectlyinthesilicon.Therawwaferisengineeredbythegrowthofanultrapure,virtuallydefect-freesiliconlayerthroughepitaxy.Inthemostadvancedlogicdevices,priortothesiliconepitaxystep,tricksareperformedtoimprovetheperformanceofthetransistorstobebuilt.Onemethodinvolvesintroducingastrainingstepwhereinasiliconvariantsuchassilicon-germanium(SiGe)isdeposited.Oncetheepitaxialsiliconisdeposited,thecrystallatticebecomesstretchedsomewhat,resultinginimprovedelectronicmobility.Anothermethod,calledsilicononinsulatortechnologyinvolvestheinsertionofaninsulatinglayerbetweentherawsiliconwaferandthethinlayerofsubsequentsiliconepitaxy.Thismethodresultsinthecreationoftransistorswithreducedparasiticeffects. Gateoxideandimplants[edit] Mainarticles:self-alignedgateanddoping(semiconductor) Front-endsurfaceengineeringisfollowedbygrowthofthegatedielectric(traditionallysilicondioxide),patterningofthegate,patterningofthesourceanddrainregions,andsubsequentimplantationordiffusionofdopantstoobtainthedesiredcomplementaryelectricalproperties.Indynamicrandom-accessmemory(DRAM)devices,storagecapacitorsarealsofabricatedatthistime,typicallystackedabovetheaccesstransistor(thenowdefunctDRAMmanufacturerQimondaimplementedthesecapacitorswithtrenchesetcheddeepintothesiliconsurface). Back-end-of-line(BEOL)processing[edit] Mainarticle:BEOL Metallayers[edit] Oncethevarioussemiconductordeviceshavebeencreated,theymustbeinterconnectedtoformthedesiredelectricalcircuits.ThisoccursinaseriesofwaferprocessingstepscollectivelyreferredtoasBEOL(nottobeconfusedwithbackendofchipfabrication,whichreferstothepackagingandtestingstages).BEOLprocessinginvolvescreatingmetalinterconnectingwiresthatareisolatedbydielectriclayers.TheinsulatingmaterialhastraditionallybeenaformofSiO2orasilicateglass,butrecentlynewlowdielectricconstantmaterialsarebeingused(suchassiliconoxycarbide),typicallyprovidingdielectricconstantsaround2.7(comparedto3.82forSiO2),althoughmaterialswithconstantsaslowas2.2arebeingofferedtochipmakers.High-κdielectricsmayinsteadbeused. Interconnect[edit] Mainarticle:interconnect(integratedcircuits) Syntheticdetailofastandardcellthroughfourlayersofplanarizedcopperinterconnect,downtothepolysilicon(pink),wells(greyish)andsubstrate(green). Historically,themetalwireshavebeencomposedofaluminum.Inthisapproachtowiring(oftencalledsubtractivealuminum),blanketfilmsofaluminumaredepositedfirst,patterned,andthenetched,leavingisolatedwires.Dielectricmaterialisthendepositedovertheexposedwires.Thevariousmetallayersareinterconnectedbyetchingholes(called"vias")intheinsulatingmaterialandthendepositingtungsteninthemwithaCVDtechniqueusingtungstenhexafluoride;thisapproachisstillusedinthefabricationofmanymemorychipssuchasdynamicrandom-accessmemory(DRAM),becausethenumberofinterconnectlevelsissmall(currentlynomorethanfour). Morerecently,asthenumberofinterconnectlevelsforlogichassubstantiallyincreasedduetothelargenumberoftransistorsthatarenowinterconnectedinamodernmicroprocessor,thetimingdelayinthewiringhasbecomesosignificantastopromptachangeinwiringmaterial(fromaluminumtocopperinterconnectlayer)andachangeindielectricmaterial(fromsilicondioxidestonewerlow-Kinsulators).Thisperformanceenhancementalsocomesatareducedcostviadamasceneprocessing,whicheliminatesprocessingsteps.Asthenumberofinterconnectlevelsincreases,planarizationofthepreviouslayersisrequiredtoensureaflatsurfacepriortosubsequentlithography.Withoutit,thelevelswouldbecomeincreasinglycrooked,extendingoutsidethedepthoffocusofavailablelithography,andthusinterferingwiththeabilitytopattern.CMP(chemical-mechanicalplanarization)istheprimaryprocessingmethodtoachievesuchplanarization,althoughdryetchbackisstillsometimesemployedwhenthenumberofinterconnectlevelsisnomorethanthree.Copperinterconnectsuseanelectricallyconductivebarrierlayertopreventthecopperfromdiffusinginto("poisoning")itssurroundings. Wafertest[edit] Thehighlyserializednatureofwaferprocessinghasincreasedthedemandformetrologyinbetweenthevariousprocessingsteps.Forexample,thinfilmmetrologybasedonellipsometryorreflectometryisusedtotightlycontrolthethicknessofgateoxide,aswellasthethickness,refractiveindex,andextinctioncoefficientofphotoresistandothercoatings.[39]Wafertestmetrologyequipmentisusedtoverifythatthewafershaven'tbeendamagedbypreviousprocessingstepsupuntiltesting;iftoomanydiesononewaferhavefailed,theentirewaferisscrappedtoavoidthecostsoffurtherprocessing.Virtualmetrologyhasbeenusedtopredictwaferpropertiesbasedonstatisticalmethodswithoutperformingthephysicalmeasurementitself.[1] Devicetest[edit] Mainarticle:Wafertesting Oncethefront-endprocesshasbeencompleted,thesemiconductordevicesorchipsaresubjectedtoavarietyofelectricalteststodetermineiftheyfunctionproperly.Thepercentofdevicesonthewaferfoundtoperformproperlyisreferredtoastheyield.Manufacturersaretypicallysecretiveabouttheiryields,butitcanbeaslowas30%,meaningthatonly30%ofthechipsonthewaferworkasintended.Processvariationisoneamongmanyreasonsforlowyield.Testingiscarriedouttopreventchipsfrombeingassembledintorelativelyexpensivepackages. Theyieldisoftenbutnotnecessarilyrelatedtodevice(dieorchip)size.Asanexample,InDecember2019,TSMCannouncedanaverageyieldof~80%,withapeakyieldperwaferof>90%fortheir5nmtestchipswithadiesizeof17.92 mm2.Theyieldwentdownto32.0%withanincreaseindiesizeto100 mm2.[40] Thefabteststhechipsonthewaferwithanelectronictesterthatpressestinyprobesagainstthechip.Themachinemarkseachbadchipwithadropofdye.Currently,electronicdyemarkingispossibleifwafertestdata(results)areloggedintoacentralcomputerdatabaseandchipsare"binned"(i.e.sortedintovirtualbins)accordingtopredeterminedtestlimitssuchasmaximumoperatingfrequencies/clocks,numberofworking(fullyfunctional)coresperchip,etc.Theresultingbinningdatacanbegraphed,orlogged,onawafermaptotracemanufacturingdefectsandmarkbadchips.Thismapcanalsobeusedduringwaferassemblyandpackaging.Binningallowschipsthatwouldotherwiseberejectedtobereusedinlower-tierproducts,asisthecasewithGPUsandCPUs,increasingdeviceyield,especiallysinceveryfewchipsarefullyfunctional(haveallcoresfunctioningcorrectly,forexample).eFUSEsmaybeusedtodisconnectpartsofchipssuchascores,eitherbecausetheydidn'tworkasintendedduringbinning,oraspartofmarketsegmentation(usingthesamechipforlow,midandhigh-endtiers).Chipsmayhavesparepartstoallowthechiptofullypasstestingevenifithasseveralnon-workingparts. Chipsarealsotestedagainafterpackaging,asthebondwiresmaybemissing,oranalogperformancemaybealteredbythepackage.Thisisreferredtoasthe"finaltest".Chipsmayalsobeimagedusingx-rays. Usually,thefabchargesfortestingtime,withpricesintheorderofcentspersecond.Testingtimesvaryfromafewmillisecondstoacoupleofseconds,andthetestsoftwareisoptimizedforreducedtestingtime.Multiplechip(multi-site)testingisalsopossiblebecausemanytestershavetheresourcestoperformmostorallofthetestsinparallelandonseveralchipsatonce. Chipsareoftendesignedwith"testabilityfeatures"suchasscanchainsora"built-inself-test"tospeedtestingandreducetestingcosts.Incertaindesignsthatusespecializedanalogfabprocesses,wafersarealsolaser-trimmedduringtesting,inordertoachievetightlydistributedresistancevaluesasspecifiedbythedesign. Gooddesignstrytotestandstatisticallymanagecorners(extremesofsiliconbehaviorcausedbyahighoperatingtemperaturecombinedwiththeextremesoffabprocessingsteps).Mostdesignscopewithatleast64corners. Deviceyield[edit] Deviceyieldordieyieldisthenumberofworkingchipsordiesonawafer,giveninpercentagesincethenumberofchipsonawafer(Dieperwafer,DPW)canvarydependingonthechips'sizeandthewafer'sdiameter.Yielddegradationisareductioninyield,whichhistoricallywasmainlycausedbydustparticles,howeversincethe1990s,yielddegradationismainlycausedbyprocessvariation,theprocessitselfandbythetoolsusedinchipmanufacturing,althoughduststillremainsaprobleminmanyolderfabs.Dustparticleshaveanincreasingeffectonyieldasfeaturesizesareshrunkwithnewerprocesses.Automationandtheuseofminienvironmentsinsideofproductionequipment,FOUPsandSMIFshaveenabledareductionindefectscausedbydustparticles.Deviceyieldmustbekepthightoreducethesellingpriceoftheworkingchipssinceworkingchipshavetopayforthosechipsthatfailed,andtoreducethecostofwaferprocessing.Yieldcanalsobeaffectedbythedesignandoperationofthefab. Tightcontrolovercontaminantsandtheproductionprocessarenecessarytoincreaseyield.Contaminantsmaybechemicalcontaminantsorbedustparticles."Killerdefects"arethosecausedbydustparticlesthatcausecompletefailureofthedevice(suchasatransistor).Therearealsoharmlessdefects.Aparticleneedstobe1/5thesizeofafeaturetocauseakillerdefect.Soifafeatureis100 nmacross,aparticleonlyneedstobe20 nmacrosstocauseakillerdefect.Electrostaticelectricitycanalsoaffectyieldadversely.Chemicalcontaminantsorimpuritiesincludeheavymetalssuchasiron,copper,nickel,zinc,chromium,gold,mercuryandsilver,alkalimetalssuchassodium,potassiumandlithium,andelementssuchasaluminum,magnesium,calcium,chlorine,sulfur,carbon,andfluorine.Itisimportantfortheseelementstonotremainincontactwiththesilicon,astheycouldreduceyield.Chemicalmixturesmaybeusedtoremovetheseelementsfromthesilicon;differentmixturesareeffectiveagainstdifferentelements. Severalmodelsareusedtoestimateyield.TheyareMurphy'smodel,Poisson'smodel,thebinomialmodel,Moore'smodelandSeeds'model.Thereisnouniversalmodel;amodelhastobechosenbasedonactualyielddistribution(thelocationofdefectivechips)Forexample,Murphy'smodelassumesthatyieldlossoccursmoreattheedgesofthewafer(non-workingchipsareconcentratedontheedgesofthewafer),Poisson'smodelassumesthatdefectivediesarespreadrelativelyevenlyacrossthewafer,andSeeds'smodelassumesthatdefectivediesareclusteredtogether.[41] Smallerdiescostlesstoproduce(sincemorefitonawafer,andwafersareprocessedandpricedasawhole),andcanhelpachievehigheryieldssincesmallerdieshavealowerchanceofhavingadefect,duetotheirlowersurfaceareaonthewafer.However,smallerdiesrequiresmallerfeaturestoachievethesamefunctionsoflargerdiesorsurpassthem,andsmallerfeaturesrequirereducedprocessvariationandincreasedpurity(reducedcontamination)tomaintainhighyields.Metrologytoolsareusedtoinspectthewafersduringtheproductionprocessandpredictyield,sowaferspredictedtohavetoomanydefectsmaybescrappedtosaveonprocessingcosts.[42] Diepreparation[edit] Mainarticles:WaferbackgrindingandDiepreparation Oncetested,awaferistypicallyreducedinthicknessinaprocessalsoknownas"backlap",[43]"backfinish"or"waferthinning"[44]beforethewaferisscoredandthenbrokenintoindividualdies,aprocessknownaswaferdicing.Onlythegood,unmarkedchipsarepackaged. Packaging[edit] Mainarticle:Integratedcircuitpackaging Plasticorceramicpackaginginvolvesmountingthedie,connectingthediepadstothepinsonthepackage,andsealingthedie.Tinybondwiresareusedtoconnectthepadstothepins.Inthe'olddays'(1970s),wireswereattachedbyhand,butnowspecializedmachinesperformthetask.Traditionally,thesewireshavebeencomposedofgold,leadingtoaleadframe(pronounced"leedframe")ofsolder-platedcopper;leadispoisonous,solead-free"leadframes"arenowmandatedbyRoHS. Chipscalepackage(CSP)isanotherpackagingtechnology.Aplasticdualin-linepackage,likemostpackages,ismanytimeslargerthantheactualdiehiddeninside,whereasCSPchipsarenearlythesizeofthedie;aCSPcanbeconstructedforeachdiebeforethewaferisdiced. Thepackagedchipsareretestedtoensurethattheywerenotdamagedduringpackagingandthatthedie-to-pininterconnectoperationwasperformedcorrectly.Alaserthenetchesthechip'snameandnumbersonthepackage. Hazardousmaterials[edit] Seealso:Healthhazardsinsemiconductormanufacturingoccupations Manytoxicmaterialsareusedinthefabricationprocess.[45]Theseinclude: poisonouselementaldopants,suchasarsenic,antimony,andphosphorus. poisonouscompounds,suchasarsine,phosphine,tungstenhexafluorideandsilane. highlyreactiveliquids,suchashydrogenperoxide,fumingnitricacid,sulfuricacid,andhydrofluoricacid. Itisvitalthatworkersshouldnotbedirectlyexposedtothesedangeroussubstances.ThehighdegreeofautomationcommonintheICfabricationindustryhelpstoreducetherisksofexposure.Mostfabricationfacilitiesemployexhaustmanagementsystems,suchaswetscrubbers,combustors,heatedabsorbercartridges,etc.,tocontroltherisktoworkersandtotheenvironment. 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Furtherreading[edit] Kaeslin,Hubert(2008),DigitalIntegratedCircuitDesign,fromVLSIArchitecturestoCMOSFabrication,CambridgeUniversityPress,section14.2. WikirelatedtoChipTechnology Externallinks[edit] WikimediaCommonshasmediarelatedtoSemiconductordevicesfabrication. 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