How a semiconductor wafer is made - USJC

FEOL (Front End of Line: substrate process, the first half of wafer processing) · Isolation · Well and channel formation · Gate oxidation and gate formation · LDD ... HOME AboutUSJC MessagefromthePresident/UMCCulture Management Corporateprofile Locations USJCHeadOffice MieFactory OurBusiness 製造 研究・開発 QualityandReliability Technology&Service Technology Low-powerCMOStechnologyDDC EmbeddedNon-VolatileMemorySolutions Plug-InFlash RF/mmWavePDK FoundryServices FoundryInformationService“MieFujitsuOnline”(MIFO) ShuttleService MieWaferFab Mie300mmproductionline HistoryofMiePlant CorporateVideo Topics PressRelease Event&Seminar UMCNews LearningaboutTechnology Howasemiconductorwaferismade CSR/Environment Environment Howasemiconductorwaferismade ManufacturingasemiconductorICrequiresasmanyashundredsofmicrofabricationsteps. Thissectionprovidesanoverviewoftheprocessflowofwaferprocessing. Supplementaryinformation» ProcessFlow MieFujitsusemiconductorundertakeswaferprocessingasafoundrycompanytomanufacturesemiconductorICs.Thissectionprovidesanoverviewoftheprocessflowofwaferprocessing. FEOL(FrontEndofLine:substrateprocess,thefirsthalfofwaferprocessing) Componentssuchastransistorsareformedonasiliconsubstrate. Isolation Wellandchannelformation Gateoxidationandgateformation LDDformation Sidewallspacers Source/drain Silicide Dielectricfilm Contactholes BEOL(BackEndofLine:interconnectprocess,thesecondhalfofwaferprocessing) ComponentsformedintheFEOLareinterconnectedwithmetalmaterialtoformcircuits. Metal-1 Metal-2 1.Isolation Transistorsareformednearthesiliconwafersurface. Toensurethateachtransistoroperatesindependently,itisnecessarytopreventinterferencewithotherneighboringtransistors.Therefore,theregionswheretransistorsaretobeformedareisolated.Thereareanumberofmethodsforthisisolation. ThetechniqueintroducedhereiscalledSTI(ShallowTrenchIsolation). “1.Isolation”more» 2.Wellandchannelformation N-MOStransistorsandp-MOStransistorsareformedinachip. Impuritiesappropriateforn-MOStransistorsandp-MOStransistorsarerespectivelyimplantedintotheSisurfaceatappropriateconcentrationsintheregionswherethetransistorsaretobeformed(n-MOS:p-well,n-channel;p-MOS:n-well,p-channel).Inthecasewheretransistorswithtwoormoredifferentvoltagesandcharacteristicsaremade,impurityimplantationofdifferentdopants/dosagesisadditionallyperformed. “2.Wellandchannelformation”more» 3.Gateoxidationandgateformation Thisstepismostimportantfromtheviewpointoftransistorcharacteristics. Agateoxidefilmgreatlyinfluencestheperformanceandreliabilityofatransistor,andshouldthereforebeahigh-densitythinfilmuniformlydistributedoverthewafersurface. Sincethesizeofthegateformedmayalsogreatlyinfluencetheperformanceofthetransistor,strictdimensionalcontrolisnecessaryinbothphotoresistpatterningandgateetching. Gateelectrodesareformedofpolysilicon(polycrystallinesilicon)byCVD. “3.Gateoxidationandgateformation”more» 4.LDDformation Toavoidadverseeffects(suchassloweroperationspeed)oftransistorminiaturization,LDDs(LightlyDopedDrains,lowdensityimpuritydrains)areformed. LDDsarealsocalledextensions. N-LDD:N-typeimpurities(e.g.,As+,P+)areimplantedinton-MOSareas. P-LDD:P-typeimpurities(e.g.,B+)areimplantedintop-MOSareas. “4.LDDformation”more» 5.Sidewallspacers AnoxidefilmisformedonlyatsidewallportionsofgatesforLDDformation(abovementioned)andsalicidation(describedbelow)ofgates,sources,anddrains. Sidewalloxidefilm:Asiliconoxidefilmisformedontheentirewafersurface. Sidewalletching:Anisotropicetching(verticaldirection)isperformedontheoxidefilmsothattheoxidefilmmaybeleftonlyongatesidewalls. “5.Sidewallspacers”more» 6.Source/drain Sourcesanddrainsareformedinn-MOSareasandp-MOSareas.Theshapesofsourcesanddrainsarethesamebecauseusualtransistorsaresymmetric.Whichisasourceoradrainisdefineddependingontheconnectiondirectionofthepowersupply. P-source/drain:P-typeimpurities(e.g.,B+)areimplantedintop-MOSareas. N-source/drain:N-typeimpurities(e.g.,As+,P+)areimplantedinton-MOSareas. “6.Source/drain”more» 7.Silicide Silicide(compoundofsiliconwithmetal)isformedongates(polysilicon),sourcesanddrains(Siwafer)asthreeMOStransistorelectrodesinordertoreducecontactresistancetometalwiringlayerstobeformedlater.Thissilicideformationalsohastheeffectofloweringtheresistanceofeachelectrode. Salicidation:Acobaltfilmisremovedselectivelybychemicaletching(Selfalignedsilicide). “7.Silicide”more» 8.Dielectricfilm Theinterconnectprocessforconnectingelementssuchastransistorsstartsfromthisstep. Dielectricfilmdeposition:AthicksiliconoxidefilmorthelikeisformedbyCVD. Dielectricfilmpolishing:Thesiliconoxidefilmispolishedforthefilmplanarizationofthewafersurface. “8.Dielectricfilm”more» 9.Contactholes Toconnectelectrodessuchasgates,sources,anddrainsoftransistorstometalwiringlayers,contactholesaremadeinthedielectricfilmandfilledwithW(tungsten). Plug-tungstenfilling:Tungstenisdepositedincontactholes. Plug-tungstenpolishing:Thesurfaceispolishedtoremoveexcesstungstenandleavetungstenonlyinthecontactholes. “9.Contactholes”more» 10.Metal-1 Adielectricfilmisdepositedasaninterlayerdielectric,atrenchpatternisformedbyphotoresistpatterningandetching,andtrenchesarefilledwithCu(copper)metalbyelectroplating. ThemethodoffillingonlythetrencheswithCuiscalledsingledamascene. Metal-1Cufilling:ACufilmisdepositedinthetrenchesbyelectroplating. Metal-1CuPolishing:ExcessCuisremovedbysurfacepolishingtoleaveCuonlyinthetrenches. “10.Metal-1”more» 11.Metal-2 Adielectricfilmisdepositedasanintermetaldielectric,atrenchandviapatternisformedbyphotoresistpatterningandetching,andtrenchesandviasarefilledwithCu(copper)metalbyelectroplating.ThemethodoffillingtrenchesandviaswithCuatthesametimeiscalleddualdamascene. Metal-2Cufilling:ACufilmisdepositedinthetrenchesandtheviasbyelectroplating. Metal-2CuPolishing:ExcessCuisremovedbysurfacepolishingtoleaveCuonlyinthetrenchesandthevias. “11.Metal-2”more» A+ A-